Integration methods for carbon films in two- and three-dimensional memories and memories formed therefrom

ABSTRACT

Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/088,668, filed Aug. 13, 2008, and titled “INTEGRATION METHODS FOR CARBON FILMS IN TWO- AND THREE-DIMENSIONAL MEMORIES AND MEMORIES FORMED THEREFROM,” which is hereby incorporated by reference herein in its entirety for all purposes.

The present application is related to U.S. Provisional Application 61/088,665 (Attorney Docket No. SD-MXA-292P-2) filed Aug. 13, 2008 and entitled “METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING” which is hereby incorporated by reference herein for all purposes.

The present application is also related to U.S. application Ser. No. ______, (Attorney Docket No. SD-MXA-292-2) filed on even date herewith and entitled “METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING” which is hereby incorporated by reference herein for all purposes.

FIELD OF THE INVENTION

The present invention relates to non-volatile memories and more particularly to integration methods for carbon films in two- and three-dimensional memories, and memories formed from such methods.

BACKGROUND

Non-volatile memories are known. As the demand for memory capabilities increases, there is a continual need to increase the number of memory cells in a memory device. However, fabricating memory cells for use in such memory devices continues to be technically challenging. Accordingly, improved methods of forming memory cells for use in memory devices are desirable.

SUMMARY

In some embodiments, the present invention provides a method of forming a memory cell which includes forming a first pillar above a substrate, the pillar comprising a first steering element and a first memory element; performing a first etch through the first pillar to form two second pillars each comprising a second steering element and a second memory element; and performing a second etch through the two second pillars to form four third pillars each comprising a third steering element and a third memory element.

In some embodiments, the present invention provides a memory cell formed by forming a first pillar above a substrate, the pillar comprising a first steering element and a first memory element; performing a first etch through the first pillar to form two second pillars each comprising a second steering element and a second memory element; and performing a second etch through the two second pillars to form four third pillars each comprising a third steering element and a third memory element.

In some embodiments, the present invention provides a method of forming a memory cell which includes forming a pillar above a substrate, the pillar comprising a steering element and a memory element; and performing multiple etches through the pillar to divide the pillar into multiple second pillars each comprising a second steering element and a second memory element.

In some embodiments, the present invention provides a memory cell formed by forming a pillar above a substrate, the pillar comprising a steering element and a memory element; and performing multiple etches through the pillar to divide the pillar into multiple second pillars each comprising a second steering element and a second memory element.

In some embodiments, the present invention provides a method of forming a memory cell which includes forming a first conductor and a second conductor; forming a diode in series with the first and second conductors; forming a memory element above the first and second conductors including forming a feature having a sidewall and depositing a carbon film on the sidewall of the feature; etching the memory element and the diode along a vertical longitudinal plane to form two memory elements and two diodes, one memory element and one diode disposed above each conductor; and forming a third conductor and a fourth conductor above the memory elements and the diodes.

In some embodiments, the present invention provides a memory cell which includes a diode layer; and a pie slice-shaped memory element coupled to the diode layer. The pie slice-shaped memory element includes a sidewall having a carbon film thereon.

In some embodiments, the present invention provides a plurality of memory cells which includes a diode layer shaped into a plurality of radially disposed pieces; and a plurality of radially disposed pie slice-shaped memory elements each coupled to a different one of the diode layer pieces. The pie slice-shaped memory elements each include a sidewall having a carbon film thereon.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same elements throughout, and in which:

FIG. 1A is an exemplary memory cell;

FIGS. 1B-1C are perspective views of exemplary memory cells in accordance with this invention;

FIG. 1D is a top view of the memory cells of FIG. 1B;

FIGS. 2A-2I illustrate cross-sectional views of a portion of a substrate during an exemplary fabrication of a single memory level in accordance with this invention;

FIG. 3 is a perspective view of exemplary memory cells in accordance with this invention; and

FIGS. 4-5 are top views of the memory cells of FIG. 3.

DETAILED DESCRIPTION

Non-volatile memories formed from reversible resistance-switching elements are known. For example, U.S. patent application Ser. No. 11/125,939, filed May 9, 2005 and titled “REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL” (hereinafter “the '939 Application”), which is hereby incorporated by reference herein in its entirety for all purposes, describes a rewriteable non-volatile memory cell that includes a diode coupled in series with a reversible resistivity-switching material such as a metal oxide or metal nitride.

Carbon films (e.g., films made from graphitic carbon, non-graphitic carbon, graphene, graphite, amorphous carbon, etc.) may exhibit reversible resistivity-switching properties, making these films candidates for integration within a three-dimensional memory array. However, film orientation and thickness may affect the switching characteristics of a carbon film. For example, when conduction occurs along the length of the carbon pi bonds of a carbon film (e.g., parallel to the plane of the film), switching may be observed.

As schematically represented in FIGS. 1A through 1D, the present invention provides a memory cell structure 100 and a manufacturing process for a carbon-based memory element. The methods of the present invention may be used with carbon material 102 that may be conformably deposited on the sidewalls of a memory cell pillar-shaped structure formed with a dielectric 104 core. The carbon material 102 may function as a reversible resistance-switching element, for example. The carbon material 102 is connected in series with a diode 106 (or other steering element) between conductors 108 and 110. Note that elements of the memory cell structures throughout the drawings are not drawn to scale and, for example, conductors 108 and 110 may be much wider than shown. Diode 106 may be a vertical p-n or p-i-n diode. In some embodiments, any rectifier device may be used in place of diode 106. In some embodiments, diode 106 may be formed from a polycrystalline semiconductor material such as polysilicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. According to the present invention, the memory cell pillar structure whose sidewalls upon which the carbon-material 102 is conformably deposited, is etched (e.g., using a highly anisotropic etch such as spacer etch) along a vertically oriented, longitudinal plane which effectively bisects the pillar lengthwise into two independent memory cells in the same space previously occupied by a single memory cell. This process thus increases the memory cell density by two times without any scaling of the pillar structure. As shown in FIG. 1B, by repeating the etching along a second vertically oriented, longitudinal plane that is approximately perpendicular to the plane of the first etch, the pillar may be divided into a total of four independent memory cells in the same space previously occupied by a single memory cell. Thus, these two processes together (as represented by FIG. 1A before and FIG. 1B after the etching) may be employed to increase the memory cell density by four times. Note that FIG. 1C is the same as FIG. 1B except the conductors 110 are included in FIG. 1C. FIG. 1D depicts a top view of the double etched memory cells 100 with the conductors omitted for clarity.

In some embodiments, the height of the memory cell 100 may be in the range of approximately 1000 A to approximately 5000 A, and preferably in the range of approximately 1200 A to approximately 2500 A. Other practicable heights may be used. In some embodiments, the height of the diode 106 portion of the memory cell 100 may be in the range of approximately 500 A to approximately 4000 A, and preferably in the range of approximately 800 A to approximately 2500 A. Other practicable diode 106 heights may be used. In some embodiments, the combined height of the carbon material 102 and dielectric 104 portion of the memory cell 100 may be in the range of approximately 200 A to approximately 2000 A, and preferably in the range of approximately 400 A to approximately 1000 A. Other practicable carbon material 102 and dielectric 104 heights may be used.

To access the “two times” more densely arranged memory cells (i.e., a single etched cell), either the word or bit lines (e.g., metal lines 108, 110 that connect to opposite ends of the memory cells 100 for reading and writing the cells) may be double patterned (to increase the number of lines in a given area to match the more densely arranged memory cells). To access the “four times” more densely arranged memory cells 100 (i.e., double etched cells), both the word and bit lines may be double patterned. Thus, existing masks for manufacturing pillar-shaped memory cells may be used with the present invention to create four times the number of memory cells 100 in the same space previously required for a single cell. This is a substantial advantage of embodiments of the present invention in that memory cell density may be doubled or quadrupled without creating a need for new masks for word and bit lines or the need to scale the memory cell pillar structure which otherwise may cause a substantial increase of the cell resistance and/or decrease the cell current which affects the cell's power consumption/requirement.

In some embodiments, where scaling may or may not be used however, for example in embodiments that use larger diameter pillars, additional etch steps may be employed to further divide the pillar along other vertically oriented longitudinal planes to create more “pie slice”-shaped memory cells. For example, using two additional longitudinal etches that are approximately perpendicular to each other but rotated about forty-five degrees relative to the first two longitudinal etches, may be used to create a total of eight relatively densely arranged memory cells. Further, as shown in FIGS. 3 to 5, additional etching may be used to create even more “pie slice”-shaped memory cells. FIG. 3 depicts a perspective view of a pillar 300 that has been etched eight times to form sixteen independent “pie slice”-shaped memory cells that each include carbon material 302 (conformed onto the surface of a dielectric core 304) in series with a diode 306 (or other steering element) and coupled to a conductor 308. Note that the top conductors (310 in FIG. 5) have been omitted for clarity. FIG. 4 depicts the same structure as FIG. 3 but from a top view perspective and FIG. 5 is the same top view but the top conductors 310 are represented. Note that only one memory cell is contacted by any one pair of bottom and top conductors 308,310. In some embodiments, the bottom and top conductors 308,310 may be spaced to align with the memory cells. Note that such embodiments or embodiments with additional independent “pie slice”-shaped memory cells may alternatively use multi-layer, staggered, and/or interwoven bit and word lines.

In some embodiments, the original diameter of the pillars 300 (before being etched into “pie slice”-shaped memory cells) may be approximately 30 nm or smaller based on the technology used to form the pillars. Presently available, cost efficient technology enables formation of pillars 300 with a diameter in the range of approximately 50 nm to approximately 1500 nm, and preferably in the range of approximately 50 nm to approximately 500 nm. Other practicable pillar diameters may be used.

In some embodiments, the height of the pillars 300 may be in the range of approximately 1000 A to approximately 5000 A, and preferably in the range of approximately 1200 A to approximately 2500 A. Other practicable pillar heights may be used. In some embodiments, the height of the diode 306 portion of the pillar 300 may be in the range of approximately 500 A to approximately 4000 A, and preferably in the range of approximately 1500 A to approximately 3000 A. Other practicable diode 306 heights may be used.

In some embodiments, the combined height of the carbon material 302 and dielectric 304 portion of the pillar 300 may be in the range of approximately 200 A to approximately 2000 A, and preferably in the range of approximately 400 A to approximately 1000 A. Other practicable carbon material 302 and dielectric 304 heights may be used.

In some embodiments, the trenches etched (or otherwise created) to form the pie-slice shaped memory cell pieces may have a width (e.g., labeled W in FIG. 4) in the range of approximately 5 nm to approximately 60 nm, and preferably in the range of approximately 10 nm to approximately 40 nm. Other practicable trench widths W may be used. For example, as with other dimensions, smaller widths may be used depending on the technology employed to form the trenches.

In some embodiments, the desired arc length (e.g., labeled A in FIG. 4) of the curved side of the individual pie-slice shaped pieces may be approximately 5nm or smaller based on the technology used to form the pillars and to etch the trenches. Presently available, cost efficient technology enables formation of pie-slice shaped pieces with an arc length A in the range of approximately 3 nm to approximately 110 nm, and preferably in the range of approximately 10 nm to approximately 25 nm (starting with a pillar 300 with an approximately 30 nm diameter). Other practicable arc lengths A may be used.

In some embodiments, the number of pieces that the pillar 300 may be divided into is a function of the desired initial pillar 300 diameter, the desired trench width W, and the desired arc length A of the curved side of the individual pie-slice shaped pieces. For example, a 60 nm diameter pillar 300 would have a circumference of approximately 188 nm (c=π·d) which if etched with two trenches, each approximately 32nm wide, would result in four pieces each with arc lengths of approximately 15 nm (≈¼[188 nm−(4·32 nm)]).

In another example, in order to form sixteen memory cells from one pillar 300, each memory cell having an arc length of approximately 5 nm, and the trench widths being approximately 5 nm, the initial diameter of the pillar may be approximately 50 nm (≈[(16·5 nm)+(16·5 nm)]/π).

Note that in these example calculations, the width W (which is actually the length of a cord instead of an arc along the circumference) is used as an approximation of the arc length of the trench along the circumference of the pillar.

In some embodiments, the “cross-talk” between the different pie-slice shaped memory cells may be prevented by choosing a gap fill material to fill the trenches that has a relatively small dielectric constant, for example in the range of approximately 1.5 to approximately 5 and preferably in the range of 2 and 3.5. Gap fill materials with other practicable dielectric constants may be used.

Turning back to FIG. 2A through 2I, methods of forming the etched pillar memory cells are now described. In accordance with one or more embodiments of the invention, novel integration schemes are provided which allow increased memory cell density of cells that use carbon films with an orientation which supports reversible resistivity-switching. For example, in some embodiments, a damascene process may be employed to form carbon films with a suitable “switching” orientation and then etching of these films may be performed to increase the density of the memory cells as mentioned above.

As described above, in some embodiments of the invention, thin carbon films may be integrated in series with a steering element, e.g., a vertical diode, to create a re-writable memory device. To achieve this, a carbon film may be vertically oriented between two metal layers or conductors, instead of horizontally oriented between two metal layers or conductors (e.g., such as in a metal-insulator-metal (MIM) planar stack). Note that the steering element (e.g., diode) may be disposed above or below the vertical oriented carbon film and in some embodiments, steering elements may be disposed above and below the vertical carbon film.

With references to FIGS. 2A through 2I, in an exemplary process provided in accordance with the present invention, a first conductor 202, which may include, for example, a tungsten, copper, aluminum, or similar first conductive layer 204 and/or a TiN or similar appropriate barrier/adhesion layer 206, may be formed and/or patterned into approximately parallel conductor (e.g., word or bit) lines 202 on a substrate (not shown) or, in a three dimensional memory, other memory cell levels (not shown). For example, conductive layer 204 may have a thickness between about 1000 A and about 1500 A, and more generally between about 800 A and about 2500 A. Barrier/adhesion layer 206 may have a thickness between about 100 A and about 250 A, and more generally between about 50 A and about 400 A. A diode layer 208 may then be deposited. As shown in FIG. 2A, a diode layer 208 may initially include, for example, an intrinsic region 210 and a negatively doped region 212. Intrinsic region 210 may have a thickness between about 800 A and about 1200 A, and more generally between about 600 A and about 1900 A. Negatively doped region 212 may have a thickness between about 100 A and about 300 A, and more generally between about 90 A and about 350 A. In some embodiments, the diode layer 208 may be patterned to form diode pillars on the conductor lines 202 as shown in FIG. 2B (and FIG. 2B′ top view). Note that only one row of three pillars on one line 202 is depicted in the drawings and one familiar with the art would understand that this depiction is intended to represent any number of rows each on a corresponding line with any number of pillars per row arranged in a consistently spaced array.

A top portion of the intrinsic region 210 may be positively doped to form a P region 213, also as shown in FIG. 2B. The structure may be coated and gap filed with a first insulating material 214 such as silicon dioxide, silicon nitride, a low k dielectric, etc., as shown in FIG. 2C. For example, between about 400 A and about 1000 A, and more generally between about 200 A and about 2000 A, of insulating material 214 may be deposited.

In some embodiments, if diode 106 is fabricated from deposited silicon (e.g., amorphous or polycrystalline), a silicide layer (not shown) may be formed on diode 106 as seeds to facilitate the crystallization of the diode 106. Therefore, the deposited silicon is in a low resistivity state, as fabricated. Such a low resistivity state allows for easier programming of memory cell 100 as a large voltage is not required to switch the deposited silicon to a low resistivity state. For example, a silicide-forming metal layer (not shown) such as titanium or cobalt may be deposited on P region 213. In some embodiments, an additional nitride layer (not shown) may be formed at a top surface of the silicide-forming metal layer. In particular, for highly reactive metals, such as titanium, an additional cap layer such as TiN layer may be formed on the silicide-forming metal layer. Thus, in such embodiments, a Ti/TiN stack is formed on top of P region 213.

A rapid thermal anneal (“RTA”) step may then be performed to form silicide regions by reaction of the silicide-forming metal layer with P region 213. The RTA may be performed at about 540° C. for about 1 minute, and causes the silicide-forming metal layer and the deposited silicon of diode 106 to interact to form a silicide layer, consuming all or a portion of the silicide-forming metal layer. As described in U.S. Pat. No. 7,176,064, titled “Memory Cell Comprising A Semiconductor Junction Diode Crystallized Adjacent To A Silicide,” which is hereby incorporated by reference herein in its entirety for all purposes, silicide-forming materials such as titanium and/or cobalt react with deposited silicon during annealing to form a silicide layer. The lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that such silicide layers may serve as “crystallization templates” or “seeds” for adjacent deposited silicon as the deposited silicon crystallizes (e.g., the silicide layer enhances the crystalline structure of silicon diode 106 during annealing). Lower resistivity silicon thereby is provided. Similar results may be achieved for silicon-germanium alloy and/or germanium diodes.

In embodiments in which a nitride layer was formed at a top surface of the silicide-forming metal layer, following the RTA step, the nitride layer may be stripped using a wet chemistry. For example, if the silicide-forming metal layer includes a TiN top layer, a wet chemistry (e.g., ammonium, peroxide, water in a 1:1:1 ratio) may be used to strip any residual TiN.

A trench, via or similar feature 216 may be formed in the first insulating material 214 above the diode pillars, as shown in FIG. 2D and carbon material 218 may be deposited in the feature 216 and on the side walls of the feature 216 as shown in FIG. 2E (and top view 2E′). For example, a carbon film 218 may be deposited on the bottom and sidewall regions of the feature 216, as well as on the (top) field regions of the first insulating material 214. Deposition on the sidewalls of the feature 216 allows the desired orientation of the carbon film 218 to be attained. Exemplary feature widths are about 20 nm to about 130 nm and exemplary feature heights are about 0.1 microns to about 2.6 microns, although other sizes may be used.

In some embodiments, to create the via, trench or similar feature 216 in the insulating material 214, a germanium, amorphous carbon or otherwise controllably etchable material is deposited, patterned and etched into a pillar (not shown). Insulating material 214 is subsequently deposited around the germanium pillar and planarized by an etch back process, chemical mechanical polishing (CMP) or the like. The insulating material 214 may be, for example, SiO₂, Si₃N₄, or any other suitable insulating and/or dielectric material. After planarization, the germanium pillar may be removed with an ashing or other etching technique to generate the feature 216 in the insulating material 214.

After the feature 216 is formed, the carbon film 218 is deposited. The carbon film 218 may be deposited by any suitable technique such as Chemical Vapor Deposition (CVD), High Density Plasma (HDP) deposition, plasma enhanced CVD, sputter deposition from an amorphous or graphite target, etc. In some embodiments, post deposition treatment(s) may be employed such as annealing in reduced pressure or oxygen environments to affect or otherwise improve the properties of the carbon film 218. Likewise, passivation of the carbon film 218 with SiN/SiON while maintaining a vacuum may be used to avoid moisture adsorption and interaction between the insulating material 214 and the carbon 218. To improve sidewall coverage, a conformal deposition process may be used in one or more embodiments.

In some exemplary embodiments, a carbon film thickness of about one monolayer to about 1000 A, and more preferably about 400 A to about 600 A, at the sidewalls of the feature 216 may be employed. Other thickness may be used.

In these or other embodiments, the interface between the carbon film 218 and the insulating material 214, such as at the sidewalls of the feature 216, may be modified to improve adhesion between the carbon film 218 and the insulating material 214. For example, carbon material deposition parameters may be adjusted so that a thin region of the carbon film 218, such as a few monolayers, in contact with the insulating material 214 is sp³ rich rather than sp² rich (as may be preferred for the remainder of the carbon film 218 in some embodiments). Additionally or alternatively, a thin “capping” layer of ALD, CVD or PECVD silicon dioxide, silicon nitride, etc., may be deposited between the carbon film 218 and the insulating material 214 to improve adhesion. Exemplary capping layer thicknesses are about 50 A to about 800 A, although other thickness ranges may be used.

In some embodiments, following formation of carbon film 218, an anneal step may be performed prior to depositing additional material. In particular, the anneal may be performed in a vacuum or the presence of one or more forming gases, at a temperature in the range from about 450° C. to about 1200° C., for about 60 sec to about 5 hours. The anneal preferably is performed in about an 80% (N₂):20% (H₂) mixture of forming gases, at about 625° C. for about one hour.

Suitable forming gases may include one or more of N₂, Ar, and H₂, whereas preferred forming gases may include a mixture having above about 75% N₂ or Ar and below about 25% H₂. Alternatively, a vacuum may be used. Suitable temperatures may range from about 200° C. to about 1200° C., whereas preferred temperatures may range from about 500° C. to about 650° C. Suitable durations may range from about 60 seconds to about 5 hours, whereas preferred durations may range from about 1 hour to about 1.5 hours. Suitable pressures may range from about 1 mT to about 760 T, whereas preferred pressures may range from about 300 mT to about 600 mT.

A queue time of preferably about 2 hours between the anneal and the deposition of additional layers preferably accompanies the use of the anneal. A ramp up duration may range from about 0.2 hours to about 1.2 hours and preferably is about 0.5 Similarly, in some embodiments, a ramp down duration also may range from about 0.2 hours to about 1.2 hours and preferably is about 0.5 hours.

Although not wanting to be bound by any particular theory, it is believed that carbon-based material may absorb water from the air over time and/or during a wet clean process. Likewise, it is believed that the moisture may increase the likelihood of de-lamination of the carbon-based material, and degradation in switching. In some cases, it also might be acceptable to have a queue time of 2 hours from the time of deposition of carbon-based material to deposition of additional layers, skipping the anneal altogether. In some cases, in-situ annealing or degas in a vacuum may be used to help to drive out moisture before the next process step. In particular, the in-situ anneal or degas in vacuum is performed in the chamber of the next processing step. Degas in vacuum may also be performed in a transfer chamber or loadlock mounted on the same platform as the process chamber. For example, if the next processing step is formation of a sidewall liner, the in-situ anneal is performed in the chamber used to form the sidewall liner. The in-situ anneal may be performed at a temperature between about 200° C. and about 350° C., more generally between about 200° C. and about 450° C., for a duration between about 1 minute to about 2 minutes, more generally between about 30 seconds and about 5 minutes, at a pressure of between about 0.1 mT to about 10 T, more generally between about 0.1 mT to about 760 T. Alternatively, the in-situ anneal may be performed in an environment containing Ar, He, or N₂, or a forming gas containing H₂ and N₂, at a flow rate of between about 1000 sccm to about 8000 sccm, more generally between about 1000 sccm and about 20000 sccm. If degas in vacuum step is used instead of in-situ annealing, the degas is performed at a pressure between about 0.1 mT to about 50 mT, and at a temperature between about room temperature to about 450° C.

Incorporation of such a post-carbon-formation-anneal preferably takes into account other layers of the memory cell, because these other memory cell layers will also be subject to the anneal. For example, the anneal may be omitted or its parameters may be adjusted where the aforementioned preferred anneal parameters would damage the other memory cell layers. The anneal parameters may be adjusted within ranges that result in the removal of moisture without damaging the layers of the annealed memory cell. For instance, the temperature may be adjusted to stay within an overall thermal budget of a memory cell being formed. Likewise, any suitable forming gases, temperatures and/or durations may be used that are appropriate for a particular memory cell. In general, such an anneal may be used with any carbon-based layer or carbon-containing material, such as layers having CNT material, graphite, graphene, amorphous carbon, etc.

Following formation of the carbon film 218, second dielectric or other insulating material 220 is then deposited onto the carbon film 218 to fill the feature 216 as shown in FIG. 2E (top view 2E′). For example, between about 400 A and about 1200 A, and more generally between about 200 A and about 2200 A of insulating material 220 may be deposited. Subsequent chemical mechanical polishing (CMP) or etch back may be employed to remove the second dielectric material 220 and the carbon film 218 from the field region of the first dielectric material 214, forming a planar surface 222 for the structure, and exposing the upper edges of the carbon film 218 on the sidewalls of the feature 216 as shown in FIGS. 2E and 2E′. In general, excess deposited carbon material, such as carbon material on the field region of the first insulating material 214, may be removed by etch back, CMP or any suitable process. In this manner, only the sidewalls and/or the bottom of the feature 216 are coated with the carbon film 218. The second dielectric material 220 may be deposited by Chemical Vapor deposition (CVD), High Density Plasma (HDP) deposition, spin-on techniques or the like. The second dielectric material 220 may be SiO₂, Si₃N₄, any combination there of, or any other suitable dielectric or insulating material.

In these or other embodiments, the interface between the carbon film 218 and the second insulating material 220 may be modified to improve adhesion between the carbon film 218 and the second insulating material 220. For example, carbon material deposition parameters may be adjusted so that a thin region of the carbon film 218, such as a few monolayers, in contact with the insulating material 220 is sp³ rich rather than sp² rich (as may be preferred for the remainder of the carbon film 218 in some embodiments). Additionally or alternatively, a thin “capping” layer of ALD, CVD or PECVD silicon dioxide, silicon nitride, etc., may be deposited between the carbon film 218 and the second insulating material 220 to improve adhesion. Exemplary capping layer thicknesses are about 50 A to about 800 A, although other thickness ranges may be used.

Following planarization of the structure, a hardmask (not shown) such as amorphous Si or TiN, may be deposited and patterned on the structure to be used to etch a first set of parallel trenches down though the pillars to the first conductors 202. A highly directional anisotropic etch (similar to a spacer etch) may be used to etch off the bottom layer of the carbon film 218. A third insulating material 224 is then used to gap fill the etched trench and the top surface may be planarized again. At this point, with the original pillars each etched into two distinct memory cells, a top conductive layer may be deposited and double patterned into top conductor lines approximately perpendicular to the bottom conductor lines 202 to form a double density memory array.

Alternatively, in some embodiments, a second hardmask (not shown), such as amorphous Si or TiN and rotated ninety degrees from the first hardmask, may be deposited and patterned on the structure (before the top conductor lines are formed) to be used to etch a second set of parallel trenches down though the pillars to the first conductors 202. Note that the second set of parallel trenches are etched approximately perpendicular to the first set of parallel trenches. In such embodiments, the original pillars are each etched into four distinct memory cells. FIG. 2F (and top view 2F′) depicts the pillars etched in two perpendicular directions.

In some embodiments, a single hardmask and a single etching step may be used to etch each of the pillars into four memory cells as depicted in FIG. 2F′. The third insulating material 224 is then used to gap fill the etched trench(es) and the top surface may be planarized again as shown in FIG. 2G.

As shown in FIG. 2H, at this point, with the original pillars each etched into two or four distinct memory cells, a top conductive layer (e.g., a tungsten, copper, aluminum, or similar conductive layer and/or a TiN or similar appropriate barrier/adhesion layer) may be deposited (e.g., using a damascene process), double patterned into top conductor lines 226 approximately perpendicular to the bottom conductor lines 202 to form a double or quadruple density memory array. Note that in the depicted quadruple density embodiment, the bottom conductor lines 202 may also be double patterned to provide an appropriate number of conductors for the additional memory cells created by the present invention. In at least one embodiment, the first and second conductors 202, 226 may be rail conductors that extend in different directions (e.g., substantially perpendicular).

FIG. 2I depicts an alternative conductor 226 structure that may be employed with the present invention. The conductor 226 structure depicted in FIG. 2H is suitable for relatively large geometry conductor lines. In this embodiment, TiN/W layers are blanket deposited, patterned using a metal etch process, and then gap-filled with dielectric. In contrast, the conductor 226 structure depicted in FIG. 2I is suitable for relatively small geometry conductor lines which may be particularly useful with the increased density memory cells of the present invention. In this embodiment, a dielectric film is initially blanket deposited, the film is patterned using a dielectric etch process, a conformal TiN liner is deposited, and then a W layer is deposited. In some embodiments, either or both of the bottom and top conductors 202, 226 may be formed using either of the two conductor structures depicted in FIGS. 2H and 2I.

Following formation of top conductors 226, the resultant structure may be annealed to crystallize the deposited semiconductor material of diodes 106 (and/or to form silicide regions by reaction of the silicide-forming metal layer with P region 213). The lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that the silicide layers may serve as “crystallization templates” or “seeds” for adjacent deposited silicon as the deposited silicon crystallizes (e.g., the silicide layer may enhance the crystalline structure of silicon diode 106 during annealing at temps of about 600-800° C.). Lower resistivity diode material thereby is provided. Similar results may be achieved for silicon-germanium alloy and/or germanium diodes.

Thus in at least one embodiment, a crystallization anneal may be performed for about 10 seconds to about 2 minutes in nitrogen at a temperature of about 600 to 800° C., and more preferably between about 650 and 750° C. Other annealing times, temperatures and/or environments may be used.

Using embodiments of the present invention, a metal-graphitic carbon-metal (MGCM) structure with double or quadruple density may be formed. Within the MGCM structure, conduction between the conductors 202, 226 may occur along vertically oriented carbon material which coats the sidewalls of the feature 216. As such, conduction may occur along the length of the carbon pi bonds of the carbon film 218, and resistivity switching may be observed. Further, such a structure reduces the likelihood of an inadvertent vertical short between the top and bottom conductors 202, 226.

In accordance with one or more embodiments of the invention, vertically oriented carbon material may be employed within the memory cells of a memory array. For example, the MGCM structure described above, or a similar carbon-based resistivity switching element, may be placed in series with a steering element to form a memory cell and the memory cell may be etched into two or four or more memory cells.

The present invention provides numerous benefits. For example, the smaller dimensions of the memory cells formed according to the methods of the present invention enables denser packing of memory arrays. The smaller memory cells have reduced operating voltage and current requirements (i.e., reduced power requirements) for read and write functions. Voltage, current, and total power requirements all scale with the memory cell size. Likewise, memory arrays formed with the smaller unit memory cells of the present invention can be programmed with less power. In some embodiments, the smaller memory cells of the present invention, operating with less power than conventional sized memory cells, may be programmed faster than conventional sized memory cells. In addition, due to the lower power consumption, less heat must be dissipated in memory arrays formed using the unit cells of the present invention.

The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims. 

1. A method of forming a memory cell, comprising: forming a first pillar above a substrate, the pillar comprising a first steering element and a first memory element; performing a first etch through the first pillar to form two second pillars each comprising a second steering element and a second memory element; and performing a second etch through the two second pillars to form four third pillars each comprising a third steering element and a third memory element.
 2. The method of claim 1, further comprising: forming first and second conductors above the substrate; wherein: two of the third pillars are formed above and coupled to the first conductor; and two of the third pillars are formed above and coupled to the second conductor.
 3. The method of claim 2, further comprising: forming third and fourth conductors above the substrate, the third and fourth conductors being substantially perpendicular to the first and second conductors.
 4. The method of claim 3, wherein: one of the third pillars is coupled to the first conductor and to the third conductor; one of the third pillars is coupled to the first conductor and to the fourth conductor; one of the third pillars is coupled to the second conductor and to the third conductor; and one of the third pillars is coupled to the second conductor and to the fourth conductor.
 5. The method of claim 1, wherein the steering element comprises a polysilicon diode.
 6. The method of claim 5, wherein the diode comprises a p-i-n diode.
 7. The method of claim 1, wherein the memory element comprises a reversible resistance-switching element.
 8. The method of claim 7, wherein the memory element comprises a carbon material.
 9. The method of claim 8, wherein the carbon material comprises one of amorphous carbon, graphene, graphite, or carbon nanotubes.
 10. The method of claim 1, wherein the first etch and the second etch are performed anisotropically.
 11. The method of claim 1 wherein the first etch and the second etch are performed concurrently.
 12. The method of claim 11 wherein the first etch and the second etch are performed using a single mask.
 13. A memory cell formed using the method of claim
 1. 14. A method of forming a memory cell, comprising: forming a pillar above a substrate, the pillar comprising a steering element and a memory element; and performing multiple etches through the pillar to divide the pillar into multiple second pillars each comprising a second steering element and a second memory element.
 15. The method of claim 14, further comprising: forming multiple first conductors above the substrate; wherein at least one second pillar is coupled to each conductor.
 16. The method of claim 15, further comprising: forming multiple second conductors above the substrate, the multiple second conductors being substantially perpendicular to the first and second conductors.
 17. The method of claim 16, wherein each second pillar is coupled to exactly one first conductor and to exactly one second conductor.
 18. The method of claim 14, wherein the steering element comprises a polysilicon diode.
 19. The method of claim 18, wherein the diode comprises a p-i-n diode.
 20. The method of claim 14, wherein the memory element comprises a reversible resistance-switching element.
 21. The method of claim 20, wherein the memory element comprises a carbon material.
 22. The method of claim 21, wherein the carbon material comprises one of amorphous carbon, graphene, graphite, or carbon nanotubes.
 23. The method of claim 14, wherein the etches are performed anisotropically.
 24. The method of claim 14 wherein the etches are performed concurrently.
 25. The method of claim 24 wherein the etches are performed using a single mask.
 26. A memory cell formed using the method of claim
 14. 27. A method of forming a memory cell comprising: forming a first conductor and a second conductor; forming a diode in series with the first and second conductors; forming a memory element above the first and second conductors including forming a feature having a sidewall and depositing a carbon film on the sidewall of the feature; etching the memory element and the diode along a vertical longitudinal plane to form two memory elements and two diodes, one memory element and one diode disposed above each conductor; and forming a third conductor and a fourth conductor above the memory elements and the diodes.
 28. The method of claim 27, wherein the diode comprises a polycrystalline diode.
 29. The method of claim 28, wherein the diode comprises a p-i-n diode.
 30. The method of claim 27, wherein the carbon film comprises a reversible resistance-switching material.
 31. A memory cell comprising: a diode layer; and a pie slice-shaped memory element coupled to the diode layer, wherein the pie slice-shaped memory element includes a sidewall having a carbon film thereon.
 32. The memory cell of claim 31 wherein the pie slice-shaped memory element is shaped in approximately a half of a pie shape.
 33. The memory cell of claim 31 wherein the pie slice-shaped memory element is shaped in approximately a quarter of a pie shape.
 34. The memory cell of claim 31 wherein the pie slice-shaped memory element is shaped in approximately an eighth of a pie shape.
 35. The memory cell of claim 31 wherein the pie slice-shaped memory element is shaped in approximately a sixteenth of a pie shape.
 36. A plurality of memory cells comprising: a diode layer shaped into a plurality of radially disposed pieces; and a plurality of radially disposed pie slice-shaped memory elements each coupled to a different one of the diode layer pieces, wherein the pie slice-shaped memory elements each include a sidewall having a carbon film thereon.
 37. The memory cells of claim 36 wherein the pie slice-shaped memory elements, each coupled to a different corresponding diode layer piece, are shaped in two approximately half pie shapes.
 38. The memory cells of claim 36 wherein the pie slice-shaped memory elements, each coupled to a different corresponding diode layer piece, are shaped in four approximately quarter pie shapes.
 39. The memory cells of claim 36 wherein the pie slice-shaped memory elements, each coupled to a different corresponding diode layer piece, are shaped in eight approximately eighth of a pie shapes.
 40. The memory cells of claim 36 wherein the pie slice-shaped memory elements, each coupled to a different corresponding diode layer piece, are shaped in sixteen approximately sixteenth of a pie shapes. 